1. Field of the Invention
The present invention relates to a lead frame with lead separation preventing means, a semiconductor package using the lead frame, and a method for fabricating the semiconductor package. More particularly, the present invention relates to a lead frame having a lead separation preventing means provided at a free end of each inner lead and adapted to increase a bonding force of the inner lead to a resin encapsulate encapsulating the lead frame to fabricate a semiconductor package, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. The present invention also relates to the semiconductor package fabricated using the lead frame, and a fabrication method for the semiconductor package.
2. Description of the Related Art
In pace with the recent trend of electronic appliances, such as electronic products for domestic and official purposes, communication appliances, and computers, toward a compactness and high performance, semiconductor packages, which are used for such electronic appliances, have been required to have a compact, highly multi-pinned, light, simple structure.
Such a requirement for semiconductor packages has resulted in developments of semiconductor packages having a structure in which the lower surface of each lead is exposed at the bottom of the resin encapsulate. For such semiconductor packages, there are bottom lead type semiconductor packages and lead end grid array type semiconductor packages. Currently, the demand of semiconductor packages having such a structure is being increased.
Similarly to typical quad-flat or bi-flat type semiconductor packages, such bottom lead type or lead end grid array type semiconductor packages can be fabricated using a well-known method. This method may involve a sawing step for cutting a wafer formed with a plurality of semiconductor chip units into pieces respectively corresponding to those semiconductor chip units, thereby separating the semiconductor chip units from one another, a semiconductor chip mounting step for mounting the semiconductor chip units on respective paddles of lead frame units integrally formed on a lead frame strip by means of a thermally-conductive adhesive resin, a wire bonding step for electrically connecting a free end of each inner lead, included in each lead frame unit, to an associated one of input/output terminals of the semiconductor chip unit mounted on the lead frame unit, a resin encapsulate molding step for molding a resin encapsulate adapted to encapsulate each semiconductor chip unit and a bonding region including bonding wires for the semiconductor chip unit, using encapsulating resin, for the protection of those elements from external environments, thereby forming semiconductor packages each including one semiconductor chip unit and one lead frame unit, a singulation step for cutting inner portions of dam bars of each lead frame unit, thereby separating the semiconductor packages from one another, and a marking step for marking characters or signs on the surface of the resin encapsulate included in each semiconductor package. In the fabrication of quad-flat or bi-flat semiconductor packages, a lead forming step is involved to form leads outwardly protruded by a considerable length from a resin encapsulate into a particular terminal shape, for example, a “J” shape. In the fabrication of bottom lead type or lead end grid array type semiconductor packages, however, it is typically unnecessary to use such a lead forming step. In bottom lead type or lead end grid array type semiconductor packages, the lower surface or free end of each lead is exposed at the bottom of the resin encapsulate. Accordingly, the exposed portion of each lead may be directly used as an external input/output terminal or attached with a solder ball to be used as an external input/output terminal.
A typical structure of such quad-flat or bi-flat semiconductor packages is illustrated in a cross-sectional view of FIG. 9. Now, this structure will be described in brief in conjunction with FIG. 9. In FIG. 9, the reference numeral 1′ denotes a semiconductor package having a quad-flat or bi-flat structure. As shown in FIG. 9, this semiconductor package includes a semiconductor chip 2 bonded to a paddle 16 by means of a thermally-conductive epoxy resin 32, and a plurality of leads 11 arranged at each of four sides or two facing sides of the paddle 16 in such fashion that they are spaced apart from the associated side of the paddle 16 while extending perpendicularly to the associated side of the paddle 16. The semiconductor package also includes a plurality of conductive wires 3 for electrically connecting the inner leads 12 to the semiconductor chip 2, respectively, and a resin encapsulate 4 for encapsulating the semiconductor chip 2 and conductive wires 3. The semiconductor package further includes outer leads 13 extending outwardly from the inner pads 12, respectively. Each outer lead 13 has a particular shape, for example, a “J” shape, so that it is used as an input/output terminal in a state in which the semiconductor package is mounted on a mother board.
FIGS. 10A and 10B are, respectively, a plan view illustrating a conventional lead frame and a cross-sectional view illustrating a bottom lead type semiconductor package fabricated using the lead frame, respectively.
As shown in FIG. 10A, the lead frame, which is denoted by the reference numeral 10′, includes a paddle 16, tie bars 15 for supporting respective corners of the paddle 16, a plurality of leads 11 arranged at each of four sides of the paddle 16 in such a fashion that they extend perpendicularly to the associated side of the paddle 16, and dam bars 17 for supporting the leads 11 and tie bars 15. Each lead 11 has an inner lead 12 encapsulated by a resin encapsulate (shown by phantom lines 21 in FIG. 10A) to be subsequently formed, and an outer lead 13 extending outwardly from the resin encapsulate. Dotted lines 23 inside the dam bars 17 represent singulation lines along which the lead frame 10′ is cut after completing a semiconductor chip mounting process, a wire bonding process, and a resin encapsulate molding process. In FIG. 10A, the reference numeral 18 denotes side rails.
The bottom lead type semiconductor package denoted by the reference numeral 1″ in FIG. 10B is that fabricated using the lead frame of FIG. 10A. As shown in FIG. 10B, the semiconductor package 1″ includes a semiconductor chip 2 bonded to the paddle 16 of the lead frame 10′, along with the leads 11 of the lead frame 10′. As mentioned above, the leads 11 are arranged at each of four sides of the paddle 16 while being spaced apart from the associated side of the paddle 16 by a desired distance. The semiconductor package 1″ also includes conductive wires 3 for electrically connecting the inner leads to the semiconductor chip 2, and a resin encapsulate 4 for encapsulating the semiconductor chip 2 and conductive wires 3. The outer lead 13 of each lead 11 has a length shorter than that of a typical quad-flat semiconductor package. Typically, the outer lead of each lead 11 is not subjected to any forming process. The lower surface of each inner lead 12 is exposed at the bottom of the resin encapsulate 4, so that it serves as an external input/output terminal, along with the lower surface of the associated outer lead 13.
In the above mentioned bottom lead type semiconductor package 1″, however, the inner leads 12, which are encapsulated in the resin encapsulate 4 in such a fashion that their lower surfaces are exposed, have a planar structure having a simple rectangular shape or an end-rounded rectangular shape. By virtue of such a planar structure of the inner leads 12, there is a high possibility for the leads 11 to be separated from the resin encapsulate 4 due to cutting impact applied thereto in a singulation process for cutting them inside the dam bars 17 or for the conductive wires 3 bonded to the leads 12 to be short-circuited due to vibrations generated in the singulation process. This problem becomes more severe in the case of a compact and highly multi-pinned package structure having an increased number of leads because the increased number of leads results in a reduction in the width of each lead, thereby reducing the area of each lead contacting the resin encapsulate.
In an operation of the semiconductor chip, problems similar to those occurring in the singulation process may occur. For example, the bonding force between the leads and the resin encapsulate 4 may be degraded due to a considerable thermal expansion difference among the paddle 16, leads 11, conductive wires 3 and resin encapsulate 4. Due to the same reason, the conductive wires 3 may be shorted-circuited.
FIG. 11 is a cross-sectional view illustrating a conventional lead end grid array type semiconductor package. This lead end grid array type semiconductor package has the same basic structure as that of the bottom lead type semiconductor package shown in FIG. 10B. Accordingly, the lead end grid array type semiconductor package of FIG. 11 will be described only in conjunction with its differences from FIG. 10B.
The semiconductor package of FIG. 11, which is denoted by the reference numeral 1′″, has leads 11 formed in accordance with a half etch process to have protrusions 19, respectively. The protrusion 19 of each lead 11 has a lower surface exposed at the bottom of the resin encapsulate 4. In order to allow the semiconductor package 1′″ to have a light, thin, simple and compact structure, the peripheral portion of the semiconductor chip 2 extends beyond the peripheral edge of the paddle 16 to a region, where the inner ends of the leads 11 are positioned. That is, the peripheral portion of the semiconductor chip 2 is positioned above the inner ends of the leads 11. The protrusion 19 of each lead 11 is attached at its lower surface with a solder ball 5 serving as an external input/output terminal. In the above mentioned conventional lead end grid array type semiconductor package 1′″, however, the inner ends of the leads 11 may come into contact with the lower surfaces of the semiconductor chip 2 in the case where the semiconductor chip 2 is bonded to the paddle 16 without keeping its accurate horizontal position, where the inner ends of the leads 11 are raised or laterally leaned during the process for injecting melted resin of high temperature and pressure to mold the resin encapsulate 4, or where the inner ends of the leads 11 are deformed, due to a careless operator, in such a fashion that they are raised. When the inner ends of the leads 11 come into contact with the lower surface of the semiconductor chip 2, a short circuit or electric leakage may occur. As a result, the semiconductor package 1′″ may operate abnormally or break down.
In the fabrication of the above mentioned conventional lead end grid array type semiconductor package 1′″, there is also a possibility for the protrusions 19 of the leads 11 to be partially or completely coated with the encapsulating resin at their lower surfaces due to a flash phenomenon which may occur in the resin molding process. The flash phenomenon is a phenomenon wherein the melted encapsulating resin spreads through gaps defined by the leads and a mold used. In such a case, it is impossible to securely attach solder balls 5 to the protrusions 19 of the leads 11. Although the attachment of solder balls 5 is achieved, these solder balls 5 may be easily detached. Furthermore, the attached solder balls 5 exhibit a degraded conduction quality. Consequently, there is a high possibility for the solder balls 5 to lose their function as external terminals.
In order to solve this problem, conventional semiconductor package fabricating methods involve a process for removing set resin film partially or completely coated over the lower surface of each protrusion 19, that is, a solder ball land 19a, after the completion of the molding process. Conventionally, this process is carried out using a chemical treating method using a strong acid such as sulfuric acid or hydrochloric acid or a mechanical treating method using metal bead impact or water jet. However, the chemical treating method involves problems of environmental pollution and requirement of purification. On the other hand, the mechanical treating method involves formation of cracks in the resin encapsulate 4, generation and accumulation of static electricity, and existence of residual flashed resin in a set state.